1. Field of the Invention
The present invention relates to a clock extracting circuit in a digital-line signal receiver which is used in an electronic exchange connected to an integrated services digital network (ISDN) or the like digital line network to extract a clock signal from the data of a signal received from the digital line network, the clock signal being used to sample the data of the signal therefrom and more particularly, to a circuit which can realize extraction of a clock signal with a small-scaled circuit configuration and with stability and accuracy at all times.
2. Description of the Related Art
In an electronic exchange having a slave synchronization type of interface such as a first-order group interface in the ISDN, the sampling of a data signal received from the ISDN requires the extraction of a clock signal having a period corresponding to a data communication rate from the data signal. Such a first-order interface is provided for each of the trunk circuits within a private branch exchange.
An internal configuration of such a first-order group interface 1 in the ISDN is exemplified in FIG. 1. The first-order group interface is connected through a network terminating unit (DSU, not shown) to an ISDN line.
As shown in FIG. 1, the first-order group interface 1 includes signal transmitting and receiving transformers 2 and 3 connected to the DSU, a signal transmitting circuit 4 for transmitting a transmission data, a signal receiving circuit 5 for receiving data from the ISDN and extracting from the received data a clock signal CLKs for sampling of the received data, a clock generating circuit 6 for generating various clock signals .PHI.1, .PHI.2, . . . to be controllably used to absorb a phase difference or jitter between a speech-channel highway 10 in the exchange and the DSU on the basis of the extracted clock signal CLKs and also for generating a clock signal CLK to be used for a time-divisional switch, "layer 1" interface 7 for transfer of data or control information between the speech-channel highway 10 and a control highway 11 within the exchange, a central control circuit 8 for receiving from the interface 7 data on a D channel in the channel structure of "23B+D" or "30B+D" and for performing protocol control of higher layers than the "layer 1 " to perform transfer of the control data between the control highway 11 and the control circuit 8, and an elastic memory 9 for absorbing the phase difference or jitter occurred when transmitting data between the speech-channel highway 10 and the DSU.
Explanation will next be briefly made by also referring to FIG. 2 as to the operation of the signal receiving circuit 5 which mainly extracts the clock signal on the basis of the data of the signal received at the first-order group interface 1 for the purpose of sampling the data of the received signal.
A data to be transmitted from terminals TxT and TxR of the transmitting transformer 2 and a data to be received at terminals RxT and RxR of the receiving transformer 3 are respectively made usually in the form of such an alternate mark inversion (AMI) code having logical levels "0" and "1" as expressed in, e.g., FIG. 2(a).
The signal receiving circuit 5, when receiving a data of such AMI code configuration through the receiving transformer 3, generates signals RxA and RxB in which logical level "0" zones correspond to zones defined by polarity changes in the level of the received data signal as shown in FIG. 2(b) and (c), and further generates such a signal CLKi as shown in FIG. 2(d) corresponding to a logical sum of these generated signals RxA and RxB (more precisely, by logically inverting them, that is, corresponding to a NAND condition). The data level of the signal CLKi is not varied in logical level "0" zones. For the purpose of alternately changing the logical level of the signal CLKi at a predetermined period even in the logical level "0" zones, a signal having a predetermined period corresponding to the alternate period of the signal CLKi is separately generated, that is, such a signal CLKs as shown in FIG. 2(e) is eventually generated at the signal receiving circuit 5. The signal CLKs thus generated is outputted from the circuit 5 to the clock generating circuit 6 as a clock signal extracted from the received data signal.
In this way, the signal receiving circuit 5, even there is a level non-change region in the received data signal of the AMI code configuration, acts to acquire the clock signal CLKs as its extraction clock which alternates always at the predetermined period corresponding to the communication rate of the data.
FIG. 3 is an example of the configuration of the prior art signal receiving circuit 5 so far widely used, which includes a clock extracting circuit for extracting or generating the clock signal CLKs on the basis of the aforementioned logical sum signal (corresponding to a clock component separation signal from the received data signal, which will be referred to as the separation clock or separation clock signal, hereinafter).
The signal receiving circuit 5 will be sequentially detailed in the following.
As shown in FIG. 3, the receiving transformer 3, which is connected to the input terminals of the signal receiver 5, is grounded at the middle point of its secondary winding.
In the signal receiver 5, a resistor R1 is connected in parallel to the secondary winding of the transformer 3 at its output terminals. Further connected to the output terminals of the transformer 3 are transistors Tr1 and Tr2 at their base electrodes through series resistors R2 and R3 respectively. The base electrodes of the transistors Tr1 and Tr2 are commonly connected to each other by means of a capacitor C1 and the emitter electrodes thereof are respectively grounded. The transistors Tr1 and Tr2 are connected at their collector electrodes with collector resistors R4 and R5 respectively and also connected thereat to a NAND gate 12. The NAND gate 12 itself is connected at its output to a clock extracting circuit 13.
The clock extractor 13, as shown in FIG. 3, comprises a resistor R6 and a capacitor C2 which form a differentiating circuit, a variable inductance L and a capacitor C3 which form a parallel resonance circuit, and a high-gain amplifier 14.
With such an arrangement as mentioned above, when the receiving transformer 3 receives such a data signal as shown in FIG. 2(a) at the input terminals RxT and RxR of its primary winding, either one of the transistors Tr1 and Tr2 is conducted in the level change regions of the received data signal so that the transistors Tr1 and Tr2 output at their collectors such signals RxA and RxB as shown in FIG. 2(b) and (c). When these signals RxA and RxB are applied to the NAND gate 12, the gate outputs the NAND signal as shown in FIG. 2(d), that is, the separation clock CLKi.
In the clock extractor 13, the differentiating circuit of the resistor R6 and capacitor C2, when receiving the separation clock CLKi from the NAND gate 12, generates a differentiation signal on the basis of the received separation clock CLKi at rising and falling timing. The generated differentiation signal is further applied to the parallel resonance circuit of the inductance L and capacitor C3 to cause a parallel resonance to induce a resonance output that in turn is then sent to the high-grain amplifier 14 to obtain such a clock signal CLKs as shown in FIG. 2(e). The clock signal thus obtained is outputted from the clock extractor 13 to the clock generator 6 as a clock extracted from the received data signal.
The "layer 1" interface 7 in FIG. 1, on the other hand, separates a synchronization bit from the received data signal in synchronism with the clock signal CLKs thus extracted, transfers B-channel data bits following the separated synchronization bit to the speech-channel highway 10 through the elastic memory 9 and also transfers D-channel data bits to the central control circuit 8.
The elastic memory 9 functions to adjust the output timing of the B-channel data bits with use of the clock signals .PHI.1, .PHI.2, . . . generated at the clock generator 6 so that a phase difference or jitter between the speech-channel highway 10 and the memory 9 is within its allowable range, and to transfer the adjusted data bits to the speech-channel highway 10. The B-channel data bits thus transferred to the speech-channel highway 10 are supplied to the time divisional switch (not shown) where the data bits are subjected to a time-divisional switching operation in synchronism with the clock signal CLK generated at the clock generator 6.
The central control circuit 8, when receiving the D-channel data bits from the interface 7, performs protocol control of higher than "layer 2" designated by the D-channel data bits to transmit and receive control data to and from the control highway 11.
The clock extractor 13 in FIG. 3, is advantageous in that the clock extractor can be made relatively simple in circuit configuration because of the use of the LC resonance circuit, but is disadvantageous, as a clock extractor to be used in such a digital line signal receiving circuit, in the following respects:
(a) When a region in the aforementioned separation clock CLKi which does not vary in logical level lasts long, the LC resonance voltage attenuates and thus it becomes difficult to obtain the desired clock signal CLKs. PA0 (b) When a trouble takes place in lines and so on, it is impossible to obtain the separation clock CLKi itself and thus it is also impossible for the clock extractor 13 to output the clock signal CLKs. That is, when such a trouble occurs, it is necessary to transmit the trouble state to the communication party but such transmission becomes impossible due to such reasons. PA0 (c) Because the clock extractor is used at high frequencies, it is indispensable to finely adjust the time constant of the L and C elements and correspondingly, these L and C elements must be very high in accuracy. PA0 (d) For the same reason as the above (because of the use of the clock extractor at high frequencies), it is difficult to manufacture a pulse coil. It is also difficult to make and mount the clock extractor in the form of an integrated circuit (IC).
For such reasons, there has been recently employed as the above clock extractor a phase locked loop (PLL) circuit which, even when a trouble occurs in signal reception, can continuously supply the normal clock signal to the clock generator 6 and which also can easily realize non-adjustment.
Such a PLL circuit, however, has an output frequency of, for example, 1.544 MHz or 2.045 MHz for the first-order group interface. Accordingly, it is impossible to directly use the output of the PLL circuit as it is as the clock signal of the time-divisional switch in an exchange handling data having a transmission rate (communication rate) of 1.536 Kbps (64 Kbps per channel, and corresponding to 24 channels). For this reason, an additional PLL circuit for adjustment of divided frequency value is needed which usually results in a large-scaled circuit.
In addition, the use of such a PLL circuit requires a fairly complicated circuit for phase comparison of a discontinuous clock separated from the received data signal.